W83792AD/AG/D/G
7. FUNCTION DECRIPPTION
7.1 General Description
The W83792D/G provides 9 analog voltage inputs, 7 fan speed inputs and output controls which
support both of PWM (Pulse Width Modulation) control and DC (Direct Current) fan control, all of them
are implemented with Smart FANTM I and Smart FANTM II. 3 sets of thermal inputs for remote
thermistor or PentiumTM 4 thermal diode outputs, and case open detection also supported in
W83792D/G. Further more, W83792D/G provides several innovative and practical functions to make
the whole system manage more efficiently and compliant with future trend of network management,
such as ASF2.0 sensor compliant, which could remote Power on/off control the system, report the
status of thermal trip, fan, and temperature limitation. Also, it is SMBus 2.0 ARP command compatible.
VID table could be selected by hardware trapping for VRM9.0 and VRD 10 specifications. 2 sets of 6
bits of VID input/output control for dual processors and 2 sets of thermal Trip input for disable VRM
module, and for the more, once the monitoring function of W83792D/G is enabled, the watch dog will
monitor every function and store the values to registers for comparison with preset ranges. If the
monitoring value exceeds the limit value, the interrupt status will be set to 1 and W83792D/G will issue
interrupt signals such as SMI# and IRQ if they are not masked off. W83792D/G also provides software
and hardware Watch Dog Timer to avoid system hang on.
7.2 Access Interface
The W83792D/G provides I2C Serial Bus for microprocessor to read/write internal registers. In the
W83792D/G, there are three serial bus addresses. Through the fi
The first serial bus address of W83792D/G has 2 hardware setting bits set by Pin15-16. The address
is 01011[pin15][pin16]X. Hence, the content of CR [48h] would be 00101110 if pin15=1 and pin16=0.
The read/write of the CPUT1/CPUT2 temperature sensor registers can be implemented through the
second address (defined at CR [4Ah] bit2-0 10011[IA1][IA0]X) and the third address (defined at
CR[4Ah] bit6-4 10010[IA1][IA0]X).rst address defined at CR[48h], all the registers can be read and
written.
7.3 The first serial bus access timing
(a) Serial bus writes to internal address register followed by the data byte
0
7
8
0
7
8
SCL
SDA
0
1
0
1
1
0
1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start By
Master
Ack
by
792D
Ack
by
792D
Frame 1
Serial Bus Address Byte
Frame 2
Internal Index Register Byte
0
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
79824DR
Stop
by
Master
Frame 3
Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
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