W83697HF/F
TABLE 4-1 UART Register Bit Map
Bit Number
Register Address Base
0
1
2
3
4
5
6
7
+ 0
Receiver
Buffer
Register
RBR
TBR
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data
Bit 5
RX Data
Bit 6
RX Data
Bit 7
BDLAB = 0
(Read Only)
+ 0
Transmitter
Buffer Register
(Write Only)
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
BDLAB = 0
+ 1
Interrupt Control ICR
Register
RBR Data
Ready
Interrupt
Enable
(ERDRI)
TBR
Empty
Interrupt
Enable
(ETBREI)
USR
Interrupt
Enable
HSR
Interrupt
Enable
0
0
0
0
BDLAB = 0
(EUSRI)
(EHSRI)
+ 2
+ 2
Interrupt Status ISR
Register
(Read Only)
"0" if
Interrupt
Pending
Interrupt
Status
Interrupt
Status
Interrupt
Status
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
Bit (0)
Bit (1)
Bit (2)**
UART FIFO
Control
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
Reversed
RX
Interrupt
Active Level Active Level
RX
Interrupt
Register
(Write Only)
(LSB)
(MSB)
+ 3
UART Control
Register
UCR
Data
Length
Select
Bit 0
Data
Length
Select
Bit 1
Multiple
Stop Bits
Enable
Parity
Bit
Enable
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Silence
Enable
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
(MSBE)
(PBE)
(EPE)
PBFE)
(SSE)
(DLS0)
(DLS1)
+ 4
+ 5
Handshake
Control
Register
HCR
USR
HSR
Data
Terminal
Ready
(DTR)
Request
to
Send
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
(RTS)
UART Status
Register
RBR Data
Ready
(RDR)
Overrun
Error
(OER)
Parity Bit
Error
(PBER)
No Stop
Bit
Error
Silent
Byte
Detected
TBR
Empty
(TBRE)
TSR
Empty
(TSRE)
RX FIFO
Error
Indication
(NSER)
(SBD)
(RFEI) **
+ 6
+ 7
Handshake
Status Register
CTS
Toggling
(TCTS)
DSR
Toggling
(TDSR)
RI Falling
Edge
(FERI)
DCD
Toggling
(TDCD)
Clear
to Send
(CTS)
Data Set
Ready
(DSR)
Ring
Indicator
(RI)
Data Carrier
Detect
(DCD)
User Defined
Register
UDR
BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+ 0
BDLAB = 1
Baudrate
Divisor Latch
Low
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+ 1
BDLAB = 1
Baudrate
Divisor Latch
High
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Publication Release Date: Feb. 2002
Revision 0.70
- 47 -
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