W83697HF
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O
8t
- TTL level bi-directional pin with 8 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
- TTL level bi-directional pin open drain output with 12 mA sink capability
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 12 mA source-sink capability
- 3.3V TTL level output pin with 12 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- CMOS level Schmitt-trigger input pin
I/O
12t
I/O
12tp3
I/OD
12t
I/O
24t
OUT
12t
OUT
12tp3
OD
12
OD
24
IN
cs
IN
t
- TTL level input pin
IN
td
- TTL level input pin with internal pull down resistor
- TTL level Schmitt-trigger input pin
IN
ts
IN
tsp3
- 3.3V TTL level Schmitt-trigger input pin
1.1 LPC Interface
SYMBOL
CLKIN
PIN
I/O
IN
FUNCTION
17
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
t
PME#
98
19
20
21
OD
Generated PME event.
PCI clock input.
12
PCICLK
LDRQ#
IN
tsp3
O
Encoded DMA Request signal.
12tp3
SERIRQ
LAD[3:0]
I/OD12t Serial IRQ input/Output.
23-26 I/O
These signal lines communicate address, control, and data
information over the LPC bus between a host and aperipheral.
12tp3
LFRAME#
LRESET#
27
28
IN
IN
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
tsp3
tsp3
Publication Release Date:Feb. 2002
Revision 0.70
- 6 -
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