W83627HF/ F/ HG/ G
PIN DESCRIPTION, continued.
TYPE
DESCRIPTION
INt
INtp3
INtd
TTL level input pin
3.3V TTL level input pin
TTL level input pin with internal pull down resistor
TTL level input pin with internal pull up resistor
TTL level Schmitt-trigger input pin
INtu
INts
INtsp3
INc
3.3V TTL level Schmitt-trigger input pin
CMOS level input pin
INcd
INcs
INcsu
CMOS level input pin with internal pull down resistor
CMOS level Schmitt-trigger input pin
CMOS level Schmitt-trigger input pin with internal pull up resistor
Note： Please refer to Section 11.2 DC CHARACTERISTICS for details.
6.1
LPC Interface
SYMBOL
PIN
I/O
FUNCTION
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz in-
put.
INt3
CLKIN
PME#
18
OD12p3
INtsp3
19
21
22
23
Generated PME event.
PCI clock input.
PCICLK
LDRQ#
SERIRQ
O12p3
Encoded DMA Request signal.
Serial IRQ input/Output.
I/O12tp3
These signal lines communicate address, control, and data in-
formation over the LPC bus between a host and a peripheral.
I/O12tp3
LAD[3：0]
24-27
INtsp3
INtsp3
INtsp3
LFRAME#
LRESET#
SUSCLKIN
29
30
75
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
32khz clock input, for CIR only.
Publication Release Date: June 09, 2006
- 13 -
Revision 2.27
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