W83310DS/DG
PRELIMINARY
- Dual Layout of W83310DS/DG and W83310S-R2 for DDR VTT Application
2.5VREF
VRAM
C1
U1
1
2
3
4
8
7
6
5
VIN
VREF2
ENABLE
VCTRL
R1
10K
1000u
GND
VREF1
3VDUAL
VOUT BOOTSEL
W83310DS/DG
DDRVTT
R2
10K
C5
100U
C2
1u
C3
1u
C4
1500u
W83310S-R2, W83310DS/DG
6. Internal Block Diagram
VCTRL
VIN
ENABLE
V
V
REF2
Control
Logic
Circuit
Control
Logic
V
OUT
REF1
BOOT_SEL
GND
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4
Publication Release Date: 2005/May
Revision 0.9