W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
4. BLOCK DIAGRAM
SATAT
SATAC
Divider
SATALOOP
USBLOOP
DOTT
DOTC
48MHz
Divider
& Sync
CPULOOP
Spread
Spectrum
XIN
XOUT
XTAL
OSC
REF 0
3
3
CPUT 0:2
CPUC 0:2
PCIELOOP
Spread
VCOCLK
Spectrum
9
9
Divider
& Snyc
SRCT 0:8
SRCC 0:8
M/N/Ratio
ROM
2
6
SE1,2
FS(A:C)
CR#_(A:F)
Latch
&POR
CK_PWRGD
ITP_EN
PCI 0:4,F0
SRC5_EN
Control
Logic
PCI_STOP#
CPU_STOP#
PD#
&Config
Register
SDATA
SCLK
I2C
Interface
Publication Release Date: December, 2006
Revision 1.0
- 3 -