W78E365/W78E365A
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
I
EA
the EA pin is high.
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
O H
PSEN
ALE
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
O H separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
RST
I L
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL1
I
XTAL2
VSS
O
I
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: ground potential.
VDD
I
POWER SUPPLY: Supply voltage for operation.
PORT 0: Function is the same as that of standard 8052.
This port also provides a multiplexed low order address/data bus during
accesses to external memory. Port 0 has internal pull-up resisters enabled by
software.
I/O D
P0.0 − P0.7
P1.0 − P1.7
P2.0 − P2.7
I/O H PORT 1: Function is the same as that of standard 8052.
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
I/O H
and P2.7 also provide the alternate function REBOOT which is H/W reboot
from LD flash.
I/O H PORT 3: Function is the same as that of the standard 8052.
P3.0 − P3.7
P4.0 − P4.7
PORT 4: A bi-directional I/O. The P4.3 also provides the alternate function
I/O H
REBOOT which is H/W reboot from LD flash.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Publication Release Date: January 10, 2007
Revision A9
- 5 -
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