W78E365/W78E365A
MODE
WFWIN
CTRL<3:0>
0010
OEN
CEN
SFRAH, SFRAL
X
SFRFD
X
Erase 64KB APROM
Program 64KB APROM
Read 64KB APROM
Erase 4KB LDROM
Program 4KB LDROM
Read 4KB LDROM
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0001
Address in
Address in
X
Data in
Data out
X
0000
0010
0001
Address in
Address in
Data in
Data out
0000
6.9.1 In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT
7
NAME
SWRESET
-
FUNCTION
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
6
Reserve.
This bit is read only. 1: CPU is running LDROM program. 0: CPU is running
APROM program.
5
LD/AP
1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM
Must be 1
4
ENAUXRAM
3
2
1
-
Reserve.
When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
1
0
FBOOTSL
FPROGEN
When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This register is protected by CHPENR register. Please write as below procedures while you would
like to write CHPCON register.
Mov CHPENR, #87h
Mov CHPENR, #59h
Anl CHPCON, #EFh ; Disable AUX-RAM
Mov CHPENR, #0h
6.10 Software Reset
Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after
time out.
Publication Release Date: January 10, 2007
- 21 -
Revision A9
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