W681512
11. TYPICAL APPLICATION CIRCUIT
VDD
0.1 uF
U2
27K
17
18
19
AO
AI-
AI+
1.0 uF
27K
14
12
13
8 KHz Frame Sy nc
FST
BCLKT
PCMT
-
DIFFERENTIAL
AUDIO IN
+
2.048 MHz
Bit Clock
27K
11
MCLK
1.0 uF 27K
20
2
PCM OUT
PCM IN
VAG
RO-
8
9
7
PCMR
BCLKR
FSR
1
3
4
5
RO+
PAI
0.01 uF
VDD
16
10
MODE SELECT
POWER CONTROL
PAO-
u/A
PUI
PAO+
-
DIFFERENTIAL
W681512
AUDIO OUT
RL > 2K ohms
+
Figure 11.1 Typical circuit for Differential Analog I/O’s
VDD
0.1 uF
U3
27K
17
AO
1.0 uF
27K
27K
14
12
13
8 KHz Frame Sync
FST
BCLKT
PCMT
18
19
AI-
AUDIO IN
2.048 MHz
Bit Clock
AI+
27K
11
MCLK
1.0 uF
20
2
PCM OUT
PCM IN
VAG
RO-
8
9
7
PCMR
BCLKR
FSR
1
3
4
5
RO+
PAI
0.01 uF
27K
27K
AUDIO OUT
RL > 2K ohms
16
10
MODE SELECT
POWER CONTROL
PAO-
u/A
PUI
PAO+
AUDIO OUT
RL > 150 ohms
100 uF
W681512
Figure 11.2 Typical circuit for Single Ended Analog I/O’s
Publication Release Date: April, 2007
Revision C14
- 29 -
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