W681512
of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered
down by connecting PAI to VDD
.
7.3. POWER MANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681512 must be 5V +/- 10%. This supply
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF
ceramic capacitor.
7.3.2. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the VAG pin. This voltage
needs to be decoupled to VSS through a 0.01 μF to a 0.1 μF ceramic capacitor.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.3.
BCLKR
FSR
Interface Mode
64 kHz to 4.096 MHz 8 kHz
Long or Short Frame Sync
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VDD
ISDN GCI with active channel B1
ISDN GCI with active channel B2
ISDN IDL with active channel B1
ISDN IDL with active channel B2
Table 7.3 PCM Interface mode selections
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8
kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC
sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when
the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The
length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge
occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin
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