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W25Q20BWSNIP 参数 Datasheet PDF下载

W25Q20BWSNIP图片预览
型号: W25Q20BWSNIP
PDF下载: 下载PDF文件 查看货源
内容描述: 具有双路和四路SPI 1.8V 2M位串行闪存 [1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI]
分类和应用: 闪存
文件页数/大小: 70 页 / 2014 K
品牌: WINBOND [ WINBOND ]
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W25Q20BW  
8.2.19 Continuous Read Mode Bits (M7-0)  
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad  
I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random  
Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place)  
to be performed on serial flash devices.  
M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8-bit  
SPI instruction code (BBh, EBh, E7h or E3h) is needed or not for the next command. When M5-4 = (1,0),  
the next command will be treated same as the current Dual/Quad I/O Read command without needing  
the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all  
commands can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be  
used.  
8.2.20 Continuous Read Mode Reset (FFh or FFFFh)  
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the  
Continuous Read Mode and return to normal SPI operation, as shown in figure 18.  
Mode Bit Reset  
for Dual I/O  
Mode Bit Reset  
for Quad I/O  
/CS  
CLK  
IO0  
Mode 3  
Mode 0  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Mode 3  
Mode 0  
FFh  
FFh  
IO1  
Don’t Care  
Don’t Care  
Don’t Care  
IO2  
IO3  
Figure 18. Continuous Read Mode Reset for Fast Read Dual/Quad I/O  
Since W25Q20BW does not have a hardware Reset pin, so if the controller resets while W25Q20BW is  
set to Continuous Mode Read, the W25Q20BW will not recognize any initial standard SPI instructions  
from the controller. To address this possibility, it is recommended to issue a Continuous Read Mode  
Reset instruction as the first instruction after a system Reset. Doing so will release the device from the  
Continuous Read Mode and allow Standard SPI instructions to be recognized.  
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The  
instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are  
needed to shift in instruction “FFFFh”.  
Publication Release Date: January 25, 2011  
- 37 -  
Preliminary - Revision B  
 
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