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W25Q20BWZPIG 参数 Datasheet PDF下载

W25Q20BWZPIG图片预览
型号: W25Q20BWZPIG
PDF下载: 下载PDF文件 查看货源
内容描述: 具有双路和四路SPI 1.8V 2M位串行闪存 [1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 70 页 / 2014 K
品牌: WINBOND [ WINBOND ]
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W25Q20BW  
To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or  
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be  
executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE and  
SRP1 bits will be cleared to 0.  
During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the  
self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).  
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be  
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle  
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status  
Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.  
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the  
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC  
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.  
Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register  
bits are 0.  
Status Register 2  
Status Register 1  
15 14 13 12 11 10  
9
8
Figure 8. Write Status Register Instruction Sequence Diagram  
Publication Release Date: January 25, 2011  
Preliminary - Revision B  
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