ISD4002 SERIES
7.2.2. SPI Diagrams
MOSI
Input Shift Register
(Loaded to Row Counter
A0-A9
only if IAB = 0)
Select Logic
Row Counter
P0-P9
OVF EOM
MISO
Output Shift Register
FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM
The following diagram describes the SPI port and the control bits associated with it.
MISO
MOSI
OVF EOM P0
P1
A3
P2
A4
P3
A5
P4
A6
P5
A7
P6
A8
P7
A9
P8
0
P9
C0
X
0
0
0
LSB
MSB
A0
A1
A2
C1
C2
C3
C4
Message Cueing (MC)
Ignore Address Bit (IAB)
Power Up (PU)
Play/Record (P/R)
RUN
FIGURE 4: SPI PORT
Publication Release Date: October 26, 2005
Revision 1.3
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