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I5116SI 参数 Datasheet PDF下载

I5116SI图片预览
型号: I5116SI
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1 16分钟期限语音记录/播放数码存储功能的设备 [SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY]
分类和应用: 存储
文件页数/大小: 88 页 / 604 K
品牌: WINBOND [ WINBOND ]
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ISD5100 – SERIES  
Conditions  
1.  
Typical values: TA = 25°C and Vcc = 3.0V.  
2.  
All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all  
specifications are 100 percent tested.  
3.  
4.  
5.  
Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).  
Differential input mode. Nominal differential input is 208 mV p-p. (0TLP)  
Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage  
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions).  
6.  
Playback and Record Duration can vary as much as –6/+4 percent over the industrial temperature  
and voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions).  
7.  
Filter specification applies to the low pass filter.  
8.  
For optimal signal quality, this maximum limit is recommended.  
When a record command is sent, TRAC = TRAC + TRACL on the first page addressed.  
9.  
10.  
The maximum signal level at any input is defined as 3.17 dB higher than the reference transmission  
level point. (0TLP) This is the point where signal clipping may begin.  
11.  
12.  
13.  
Measured at 0TLP point for each gain setting. See the ANA IN table and AUX IN table on pages 54  
and 55 respectively.  
0TLP is the reference test level through inputs and outputs. See the ANA IN table and AUX IN table  
on pages 54 and 55 respectively.  
Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth.  
14. For die, only typical values are applicable.  
10.4. CHARACTERISTICS OF THE I2C SERIAL INTERFACE  
The I2C interface is for bi-directional, two-line communication between different ICs or modules. The  
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a  
positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not  
busy.  
Bit transfer  
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable  
during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted  
as a control signal.  
Publication Release Date: October, 2003  
- 69 -  
Revision 0.2  
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