ISD5100 – SERIES
I2C INTERFACE TIMING
STANDARD-MODE
FAST-MODE
UNIT
PARAMETER
SCL clock frequency
SYMBOL
MIN.
0
MAX.
100
-
MIN.
0
MAX.
400
-
kHz
fSCL
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
4.0
0.6
µs
tHD-STA
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
-
-
-
1.3
0.6
0.6
-
-
-
µs
µs
µs
tLOW
tHIGH
Set-up time for a repeated START
condition
tSU-STA
Data set-up time
250
-
-
100(1)
-
ns
ns
tSU-DAT
tr
(2)
(2)
Rise time of both SDA and SCL
signals
1000
20 + 0.1Cb
300
Fall time of both SDA and SCL
signals
-
300
20 + 0.1Cb
300
ns
tf
Set-up time for STOP condition
4.0
4.7
-
-
0.6
1.3
-
-
µs
µs
tSU-STO
tBUF
Bus-free time between a STOP and
START condition
Capacitive load for each bus line
-
400
-
-
400
-
pF
V
Cb
Noise margin at the LOW level for
each connected device (including
hysteresis)
0.1 VDD
0.1 VDD
VnL
Noise margin at the HIGH level for
each connected device (including
hysteresis)
0.2 VDD
-
0.2 VDD
-
V
VnH
1. A Fast-mode I2C-interface device can be used in a Standard-mode I2C-interface system, but the
requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line; tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C -interface specification)
before the SCL line is released.
2. Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are
allowed.
Publication Release Date: October, 2003
- 57 -
Revision 0.2
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