ISD5100 – SERIES
7.6. PIN DETAILS
7.6.1. Digital I/O Pins
SCL (Serial Clock Line)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor
to Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged
over the Serial Data Line.
SDA (Serial Data Line)
The Serial Data Line carries the data between devices on the I2C interface. Data must be valid on
this line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is
a bi-directional line requiring a pull-up resistor to Vcc.
RAC (Row Address Clock)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency,
the duration of this period is 256 ms. There are 2048 pages of memory in the ISD5116 devices, 1024
pages in the ISD5108, and 572 pages in the ISD5104. RAC stays HIGH for 248 ms and stays LOW
for the remaining 8 ms before it reaches the end of the page.
1 ROW
RAC Waveform
During 8 KHz Operation
256 msec
TRAC
8 msec
TRACL
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing
mode. See the Timing Parameters table on page 64 for RAC timing information at other sample
rates. When a record command is first initiated, the RAC pin remains HIGH for an extra TRACML period,
to load sample and hold circuits internal to the device. The RAC pin can be used for message
management techniques.
1 ROW
RAC Waveform
During Message Cueing
@ 8KHz Operation
500 usec
TRACM
15.6 us
TRACML
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