ISD5100 – SERIES
WaitSCLHigh
SendByte(0x40)
WaitACK
- Exit Digital Mode Command
WaitSCLHigh
I2Cstop
Notes
1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address
Byte will be ignored.
2. I2C bus is released while erase proceeds. Other devices may use the bus until it is time to
execute the STOP command that causes the end of the Erase operation.
3. Host processor must count RAC cycles to determine where the chip is in the erase process,
one row per RAC cycle. RAC pulses LOW for 0.25 millisecond at the end of each erased
row. The erase of the "next" row begins with the rising edge of RAC. See the Digital Erase
RAC timing diagram on page 51.
4. When the erase of the last desired row begins, the following STOP command (Command Byte
= 80 hex) must be issued. This command must be completely given, including receiving the
ACK from the Slave before the RAC pin goes HIGH at the end of the row.
Publication Release Date: October, 2003
- 39 -
Revision 0.2
WINBOND [ WINBOND ]
