BRIGHT
Microelectronics
Inc.
Preliminary BM29F400T/BM29F400B
AC CHARACTERISTICS
Read-Only Operations
DESCRIPTION
-90
-120 -150 UNIT
PARAMETER SYM.
TEST SETUP
JEDEC
Standard
(2)
Read Cycle Time
Min.
90
90
120
120
150
150
nS
nS
t
t
t
t
AVAV
AVQV
RC
Address to Output Delay
Max.
ACC
CE = VIL
= VIL
OE
Chip Enable to Output Delay
Max.
Max.
90
35
120
50
150
55
nS
nS
t
t
t
t
ELQV
GLQV
CE
OE
= VIL
OE
Output Enable to Output
Delay
Chip Enable to Output High
Z(3,4)
Max.
20
20
0
30
30
0
35
35
0
nS
nS
nS
t
t
t
t
t
t
EHQZ
GHQZ
AXQX
HZ
DF
OH
Output Enable to Output High
Z(2,3)
Output Hold Time from
Min.
Addresses,
or
,
OE
CE
Whichever Occurs First
t
Max.
Max.
20
5
20
5
20
5
mS
nS
READY
Pin Low to Read
RESET
(4)
Mode
t
t
ELFL
ELFH
CE to BYTE Switching
Low or High
Notes:
1. Test Conditions: Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 20 nS; Input pulse levels: 0.45 V to 2.4 V
2. Timing measurement reference level
Input: 0.8 and 2.0 V; Output: 0.8 and 2.0 V
3. Output driver disable time.
4. Not 100% tested.
5.0 V
2.7 KOhm
IN3064 or
Equivalent
DEVICE
UNDER
TEST
CL
6.2 KOhm
Diodes = IN3064
or Equivalent
Figure 7. Test Condition
Note: CL = 100 pF including jig capacitance.
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