WT7527V
Rev. 1.01
BLOCK DIAGRAM
WT7527V
VCC
Power On Reset
PWR
PWR
VCCI
38ms
4ms
clr
delay
PSONB
debounce
1.2V ~ 1.8V
Bandgap
VREF = 1.2V
Reference
75ms / 600ms
delay
clr
VREF = 1.2V
-
UN
V33
+
Internal
VCCI = 3.6V
Power
-
OV
+
-
UN
V5
V12A
V12B
+
PWR
-
OV
+
OSC
CLK
-
UN
+
-
OV
clr
+
60us
-
debounce
UN
+
-
OV
+
R
S
FPOB
clr
14us
Q
debounce
-
OV
VX
+
PGO
clr
73us
300ms
delay
-
clr
PGI
+
debounce
V12A
-
I33
+
V12A
IREF * 8
V12A
VREF = 1.2V
+
V12A
IREF=VREF / RI
-
-
+
RI
I5
IREF * 8
V12A
-
I12A
+
IREF * 8
clr
20ms
V12A
debounce
-
I12B
+
IREF * 8
Weltrend Semiconductor, Inc.
Page 4
WELTREND [ WELTREND SEMICONDUCTOR ]
