:
WCSS0232V1P
Switching Waveforms (continued)
Read/Write Cycle Timing[14,15,16, 17]
Single Read
tCYC
Single Write
tCH
Unselected
Burst Read
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADS
tADVS
tADH
tAS
tADVH
WD2
ADD
RD1
RD3
tAH
GW
WE
CE1
tWS
tWS
tWH
tCES
tCEH
tWH
CE1 masks ADSP
CE2
CE3
tCES
tCEH
tDOE
tCES
tCEH
OE
tOEHZ
tDS
tDH
tDOH
See Note 17
tOELZ
tCO
2a
Out
3b
Out
3c
Out
3a
Out
3d
Out
Data-
In/Out
1a
1a
2a
In
Out
TCHZ
= UNDEFINED
= DON’T CARE
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
11