WCSS0418V1P
Pin Configurations
(continued)
119-Ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
DQP
b
A
A
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
V
ss
V
SS
V
SS
V
SS
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
NC
NC
5
A
A
A
V
SS
V
SS
V
SS
V
ss
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
V
SS
A
NC
6
A
CE
3
A
DQP
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC
ZZ
V
DDQ
Pin Definitions
Name
A
[17:0]
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the
2-bit counter.
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW
[1:0]
and BWE).
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
2
Synchronous and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
2
to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input-
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
Synchronous ments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
[17:0]
Synchronous is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
I/O
Input-
Synchronous
BW
[1:0]
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
ADV
ADSP
Document #: 38-05247
Page 3 of 17
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
