WCSS0418V1F
Switching Characteristics
Over the Operating Range
[10]
-117
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CDV
t
DOH
t
ADS
t
ADH
t
WES
t
WEH
t
ADVS
t
ADVH
t
DS
t
DH
t
CES
t
CEH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
t
EOV
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWS
[1:0]
, GW, BWE Set-Up Before CLK Rise
BWS
[1:0]
, GW, BWE Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
Chip Enable Hold After CLK Rise
Clock to High-Z
[11, 12]
Clock to Low-Z
[11, 12]
OE HIGH to Output High-Z
[11, 13]
OE LOW to Output
Low-Z
[11, 13]
0
3.5
OE LOW to Output Valid
0
3.5
0
3.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
3.5
0
3.5
Description
Min.
8.5
3.0
3.0
2.0
0.5
7.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
3.5
Max.
Min.
10
4.0
4.0
2.0
0.5
8.0
-100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a) and (b) of AC Test Loads.
11. t
CHZ
, t
CLZ
, t
EOHZ
, and t
EOLZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state
voltage.
12. At any given voltage and temperature, t
CHZ
(max.) is less than t
CLZ
(min.).
13. This parameter is sampled and not 100% tested.
Document #: 38-05245 Rev. **
Page 9 of 18
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
