WMS512K8-XXX
White Electronic Designs
TIMING WAVEFORM - READ CYCLE
tRC
ADDRESS
CS#
tAA
tRC
ADDRESS
DATA I/O
tAA
tACS
tCLZ
tCHZ
tOH
OE#
PREVIOUS DATA VALID
DATA VALID
tOE
tOLZ
tOHZ
READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH)
DATA I/O
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2 (WE# = VIH)
WRITE CYCLE - WE# CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
CS#
tAS
tWP
WE#
tOW
tDH
tDW
DATA VALID
tWHZ
DATA I/O
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
tWC
ADDRESS
tAW
tAS
tAH
tCW
CS#
tWP
WE#
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2004
Rev. 10
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
