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WED8L24258V10BC 参数 Datasheet PDF下载

WED8L24258V10BC图片预览
型号: WED8L24258V10BC
PDF下载: 下载PDF文件 查看货源
内容描述: 异步SRAM , 3.3V , 256Kx24 [Asynchronous SRAM, 3.3V, 256Kx24]
分类和应用: 静态存储器
文件页数/大小: 5 页 / 443 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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WED8L24258V  
Asynchronous SRAM, 3.3V, 256Kx24  
DESCRIPTION  
FEATURES  
The WED8L24258VxxBC is a 3.3V, twelve megabit SRAM con-  
structed with three 256Kx8 die mounted on a multi-layer laminate  
substrate. With 10 to 15ns access times, x24 width and a 3.3V  
operatingvoltage,theWED8L24258Visidealforcreatingasinglechip  
memory solution for the Motorola DSP5630x or a two chip solution  
for the Analog Devices SHARCTM DSP.  
n 256Kx24 bit CMOS Static  
n Random Access Memory Array  
• Fast Access Times: 10, 12, and 15ns  
• Master Output Enable and Write Control  
• Three Chip Enables for Byte Control  
• TTL Compatible Inputs and Outputs  
• Fully Static, No Clocks  
The single or dual chip memory solutions offer improved system  
performance by reducing the length of board traces and the number  
ofboardconnectionscomparedtousingmultiplemonolithicdevices.  
n Surface Mount Package  
• 119 Lead BGA (JEDEC MO-163), No. 391  
• Small Footprint, 14mmx22mm  
• Multiple Ground Pins for Maximum Noise Immunity  
n Single +3.3V (±5%) Supply Operation  
n DSP Memory Solution  
The JEDEC Standard 119 lead BGA provides a 69% space savings  
over using six 256Kx4, 300 mil wide SOJs and the BGA package  
has a maximum height of 110 mils compared to 148 mils for the SOJ  
packages. The BGA package also allows the use of the same  
manufacturingandinspectiontechniquesastheMotorolaDSP,which  
is also in a BGA package.  
• Motorola DSP5630x  
• Analog Devices SHARCTM  
FIG. 1  
PIN CONFIGURATION  
PINSYMBOLS  
PIN NAMES  
A0-17  
E
Address Inputs  
Chip Enable  
1
2
3
4
5
6
7
W
Master Write Enable  
Master Output Enable  
Common Data Input/Output  
Power (3.3V ±5%)  
Ground  
A
B
C
D
E
F
G
H
J
NC  
NC  
AO  
A5  
NC  
A1  
A6  
E2  
A2  
E0  
NC  
A3  
A7  
E3  
A4  
A8  
NC  
NC  
NC  
I/00  
I/01  
I/02  
I/03  
I/04  
I/05  
NC  
I/06  
I/07  
I/08  
I/09  
G
DQ0-23  
VCC  
GND  
NC  
I/012  
I/013  
I/014  
I/015  
I/016  
I/017  
NC  
I/018  
I/019  
I/020  
I/021  
I/022  
I/023  
NC  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
NC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
NC  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
NC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
NC  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
No Connection  
BLOCK DIAGRAM  
K
L
18  
M
N
P
R
T
A0  
-A17  
G
W
256K x 24  
Memory  
Array  
VCC I/010  
A17  
A12  
I/011  
NC  
DQ0-7  
E0  
E2  
E3  
A9  
A10  
W
A11  
DQ8-15  
UNC  
A13  
A14  
G
A15  
A16  
NC  
DQ16-23  
1
July 2002 Rev. 0A  
ECO #15432  
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com