W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
CAS LATENCY (CL)
ꢀhe CAS latency (CT) is defined by bits M4–M6, as shown
in Figure 5. CT is the delay, in clock cycles, between the
registration of a READ command and the availability of
the first bit of output data. ꢀhe CT can be set to 3, 4, 5,
or 6 clocks, depending on the speed grade option being
used.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AT). ꢀhis feature allows the READ
command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AT clocks.
Examples of CT = 3 and CT = 4 are shown in Figure 6;
both assume AT = 0. If a READ command is registered
at clock edge n, and the CT is m clocks, the data will be
available nominally coincident with clock edge n+m (this
assumes AL = 0).
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
FIGURE 6 – CAS LATENCY (CL)
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUꢀ
D
OUꢀ
D
OUꢀ
DOUꢀ
n + 3
DQ
n
n + 1
n + 2
CT = 3 (AT = 0)
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUꢀ
D
OUꢀ
D
OUꢀ
DOUꢀ
n + 3
DQ
n
n + 1
n + 2
CT = 4 (AT = 0)
Burst length = 4
Posted CAS# additive latency (AT) = 0
t
t t
AC, DQSCK, and DQSQ
ꢀRANSIꢀIONING DAꢀA
DON’ꢀ CARE
Shown with nominal
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
