PCMCIA Flash Memory Card
FLG Series
White Electronic Designs
PINOUT
Pin
1
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
I/O
Function
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
I/O
Function
Ground
Active
2
I/O
Data bit 3
O
I/O
I/O
I/O
I/O
I
Card Detect 1
Data bit 11
LOW
3
I/O
Data bit 4
4
I/O
Data bit 5
Data bit 12
5
I/O
Data bit 6
Data bit 13
6
I/O
Data bit 7
Data bit 14
7
I
I
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
LOW
LOW
Data bit 15
8
I
Card Enable 2
Voltage Sense 1
Reserved
LOW
N.C.
9
I
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I
RFU
A9
I
RFU
Reserved
A8
I
A17
I
I
I
I
I
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
256KB(2)
512KB(2)
1MB(2)
A13
A14
WE#
RDY/BSY#
VCC
I
A18
I
A19
I
LOW
N.C.
A20
2MB(2)
O
A21
4MB(2,3)
VCC
VPP1
A16
A15
A12
A7
VPP2
A22
I
I
I
8MB(2,3)
N.C.
I
A23
I
A24
I
N.C.
I
A25
I
N.C.
A6
I
VS2
O
I
N.C.
A5
I
RST
N.C.
A4
I
I
Wait#
RFU
O
Extended Bus cycle
Reserved
LOW(1)
A3
A2
I
REG#
BVD2
BVD1
DQ8
I
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
A1
I
O
(1)
(1)
A0
I
O
DQ0
DQ1
DQ2
WP
I/O
I/O
I/O
O
I/O
I/O
O
Data bit 1
DQ9
Data bit 9
Data bit 2
DQ10
CD2#
GND
Data bit 10
Write Potect
Ground
HIGH
O
Card Detect 2
Ground
LOW
GND
Notes:
1.
2.
3.
WAIT#, BVD1 and BVD2 are driven high for compatibility
Shows density for which specified address bit is MSB. Higher order address bits are no connects (i.e. 4MB A21 is MSB A22 - A25 are NC).
For the 3MB card the memory will wrap at the 4MB boundary, for the 5MB card the memory will wrap at the 8MB boundary.
MECHANICAL
Interconnect area
1.6mm 0.05
10.0mm MIN
3.0mm MIN
(0.063”)
(0.400”)
1.0mm 0.05
(0.039”)
Substrate area
54.0mm 0.10
(2.126”)
85.6mm 0.20
(3.370”)
1.0mm 0.05
(0.039”)
10.0mm MIN
(0.400”)
3.3mm T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June, 2003
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
