White Electronic Designs
2Mx16 Flash MODULE, SMD 5962-97610
FEATURES
Access Times of 90, 120, 150ns
Packaging:
•
56 lead, Hermetic Ceramic, 0.520" CSOP
(Package 207).
Fits standard 56 SSOP footprint.
•
44 pin Ceramic SOJ (Package 102)**
•
44 lead Ceramic Flatpack (Package 208)**
Sector Architecture
•
32 equal size sectors of 64KBytes each
•
Any combination of sectors can be erased.
Also supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx16; User Configurable as 2 x 2Mx8
Commercial, Industrial, and Military Temperature
Ranges
5 Volt Read and Write. 5V ± 10% Supply.
WF2M16-XXX5
PRELIMINARY*
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation.
RESET# pin resets internal state machine to the
read mode.
Ready/Busy (RY#/BY#) output for detection of
program or erase cycle completion.
Multiple Ground Pins for Low Noise Operation
* This product is under development, is not qualified or characterized and is subject to
change without notice.
** Package to be developed.
Note: For programming information refer to Flash Programming 16M5 Application Notes.
FIGURE 1 – PIN CONFIGURATIONS
WF2M16-XDAX5
56 CSOP
TOP VIEW
CS1#
A12
A13
A14
A15
NC
CS2#
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY#
OE#
WE#
NC
I/O13
I/O5
I/O12
I/O4
V
CC
WF2M16-XXX5
44 CSOJ (DL)**
44 FLATPACK (FL)**
TOP VIEW
CS1#
A12
A13
A14
A15
NC
CS2#
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY#
OE#
WE#
NC
I/O13
I/O5
I/O12
I/O4
V
CC
PIN DESCRIPTION
I/O
0-15
A
0-20
WE#
CS
1-2
#
OE#
VCC
VSS
RY/BY#
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Ready/Busy
Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
#RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
#RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
BLOCK DIAGRAM
I/O
0-7
RESET#
WE#
OE#
A
0-20
RY / B Y #
I/O
8-1
2M x 8
2M x 8
** Package to be developed.
CS
1#
CS
2#
NOTE:
1. RY/BY# is an open drain output and should be pulled up to Vcc with an external resistor.
2. Address compatible with Intel 2M8 56 SSOP.
April 2004
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
