WMF2M8-XXX5
White Electronic Designs
FIGURE 8 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
XXX for program PA for program
SA for sector erase
XXX for chip erase
XXX for erase
Data Polling
PA
Addresses
t
t
WC
AS
tAH
t
WH
WE#
OE#
t
GHEL
t
WHWH1 or 2
t
CP
CS#
Data
t
t
WS
CPH
t
BUSY
t
DS
t
DH
D
DQ7
OUT
t
RH
AO for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of a four bus cycle sequence.
May 2004
Rev. 6
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
