WMS256K16-XXX
White Electronic Designs
TIMING WAVEFORM - READ CYCLE
tRC
tRC
ADDRESS
CS#
ADDRESS
DATA I/O
tAA
tAA
tOH
tCHZ
tACS
PREVIOUS DATA VALID
DATA VALID
LB#, UB#
tBHZ
tBA
READ CYCLE 1 (CS# = OE# = VIL, UB# or LB# = VIL, WE# = VIH
)
tBLZ
tCLZ
OE#
tOE
tOHZ
tOLZ
DATA I/O
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2 (WE# = VIH
)
WRITE CYCLE - WE# CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
CS#
tBW
LB#, UB#
tAS
tWP
WE#
tOW
tDH
tWHZ
tDW
DATA I/O
DATA VALID
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
WRITE CYCLE - LB#, UB# CONTROLLED
tWC
tWC
ADDRESS
ADDRESS
tAW
tAW
tAH
tAH
tAS
tAS
tCW
tCW
CS#
LB#, UB#
WE#
CS#
tBW
tBW
LB#, UB#
tWP
tWP
WE#
tDW
tDH
tDW
tDH
DATA I/O
DATA I/O
DATA VALID
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
WRITE CYCLE 3, LB#, UB# CONTROLLED
August 2004
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
