TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
-55°C
≤
T
C
≤
+125°C
V
SS
= 0 V dc
+4.5 V dc
≤
V
CC
≤
+5.5 V dc
unless otherwise specified
Group A
subgroups
Device
types
Min
Limits
Max
Unit
Read cycle timing characteristics - Continued.
Address access timing
t
AA
See figure 4
9,10,11
01
02
03
04
05,11
06,12
07,13
08,14
09,15
10,16
17,19
18,20
01-04
05-10
11-20
01
02
03
04
05,11
06,12
07,13
08,14
09,15
10,16
17,19
18,20
01
02
03
04
05-07
11-13
08,14
09,15
10,16
17,19
18,20
01,02
03,04
05-07
11-13
08-10
14-20
10
10
4
4
2
2
5
0
0
120
100
85
70
55
45
35
25
20
17
15
12
60
50
40
35
25
25
12
10
9
8
7
120
100
85
70
55
45
35
25
20
17
15
12
ns
Output hold from address
change
Chip select access timing
t
OH
See figure 4
9,10,11
ns
t
ACS
See figure 4
9,10,11
ns
Output enable to output
valid
t
OE
See figure 4
9,10,11
ns
Chip select to output in
low impedence 4/
t
CLZ
See figure 4
9,10,11
ns
See footnote at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
A
REVISION LEVEL
R
5962-94611
SHEET
8
DSCC FORM 2234
APR 97
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
