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SCA3000-E05-1 参数 Datasheet PDF下载

SCA3000-E05-1图片预览
型号: SCA3000-E05-1
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Circuit]
分类和应用:
文件页数/大小: 45 页 / 1038 K
品牌: VTI [ VTI TECHNOLOGIES ]
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SCA3000 Series  
SCA3000-L01  
Table 2. Available measurement modes for SCA3000.  
Available measurement  
modes  
SCA3000-D01  
SCA3000-D02  
SCA3000-E01  
SCA3000-E02  
Measurement  
mode  
SCA3000-D03  
SCA3000-E04  
SCA3000-E05  
Default after power-on  
or reset  
Measurement  
mode  
Measurement  
mode  
Measurement  
mode  
Measurement  
mode  
Measurement  
mode  
Bypass  
Narrow band  
measurement  
mode  
Narrow band  
measurement  
mode  
Narrow band  
measurement  
mode  
Bypass  
Optional measurement  
mode 1  
measurement  
mode  
Not available  
Not available  
measurement  
mode  
Wide band  
measurement  
mode  
Wide band  
measurement  
mode  
Optional measurement  
mode 2  
Not available  
Not available  
Not available  
2.2.1.1 Bypass measurement mode  
In bypass measurement mode, the signal bandwidth of the SCA3000 is extended by bypassing the  
low-pass filter in signal channel. As a result of a wider measurement bandwidth, the noise level is  
higher.  
2.2.1.2 Narrow band measurement mode  
In narrow band measurement mode, the signal bandwidth of the SCA3000 is reduced by increasing  
low-pass filtering in signal channel. In addition, the output data rate is halved due to decimation. As  
a result of a narrower signal bandwidth, the noise level is lower.  
2.2.1.3 Wide band measurement mode  
In wide band measurement mode, the SCA3000 signal channel low-pass filtering pass band is  
widened. As a result of a wider measurement bandwidth, the noise level is higher.  
2.2.2 Usage  
The optional measurement modes can be enabled by setting the bits called MODE_BITS in MODE  
register to "010" or "001". See section 3.4 for MODE register details.  
Acceleration data can be read from data output registers X_LSB, X_MSB, Y_LSB, Y_MSB, Z_LSB  
and Z_MSB in all measurement modes. Each of these registers can be read one by one or using  
the decrement register read, which is described in section 4.1.3.2 for SPI and 4.2.1.3 for I2C  
interface. See section 3.3 for output register details.  
2.2.2.1 Overflow condition  
Since acceleration data registers have no limiter, the possible overflow needs to be detected using  
bits [B7, B6, B5]. If bits [B7, B6, B5] are ‘011’ or ‘100’, data overflow has occurred (see Table 3).  
This applies for all acceleration output registers (X_LSB … Z_MSB and BUF_DATA).  
Table 3. Overflow bit patterns in acceleration data registers (X_LSB … Z_MSB and BUF_DATA).  
Byte  
MSB byte  
LSB byte  
Bit number  
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2:B0  
Acceleration data bit Sign d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0  
Data overflow on  
0
1
1
x
x
x
x
x
x
x
x
x
x
xxx  
xxx  
positive acceleration  
Data overflow on  
negative  
1
0
0
x
x
x
x
x
x
x
x
x
x
acceleration  
x = ignore  
In case of overflow, the output register value must be discarded. When an overflow is detected, the  
bit pattern ‘0101 1111 1111 1xxx’ is used for positive accelerations and ‘1010 0000 0000 0xxx’ for  
VTI Technologies Oy  
www.vti.fi  
PRELIMINARY - Subject to changes  
Doc.Nr. 8257300A.06  
8/ 45  
Rev.A.06