CMA3000-D0X Series
Address: 09h
Register name: MDTHR, Motion detection threshold value register
Initial
Value
0
8h
Bits
Mode
RW
Name
Description
Reserved
7
6:0
MDTHR[6:0] Motion detection threshold level absolute value. See
detailed bit level weighting in Table 5 (bits [6:0])
Table 5. Bit level description in [mg] for motion detection threshold of CMA3000-D01.
G_RANGE
0
Range
8g
B7
x
B6
B5
B4
B3
B2
286
B1
143
B0
4571 2286 1142 571
1/14 = 71 mg
x=not used bit
Address: 0Ah
Register name: MDFFTMR, Motion and free fall detection time register
Initial Value
Bits
7:4
3:0
Mode
Name
Description
Motion detection timer bits
Free fall detection timer bits
RW
RW
3h
3h
MDTMR[3:0]
FFTMR [3:0]
The LSB bit weighting for MDTMR and FFTMR bits are converted to seconds by using the currently
configured CMA3000 output data rate (ODR), as follows:
MDTMRLSB[sec] = 1 / ODR[Hz], and
FFTMRLSB[sec] = 1 / ODR[Hz]
Were the ODR is the currently configured CMA3000 output data rate, which is defined by MODE
bits (bits [3:1] in CTRL register). An example for CMA3000-D01 timer bit weighting is presented in
Table 6 below.
Table 6. An example for CMA3000-D01 MDTMR and FFTMR bit level descriptions in [ms].
Timer
MDTMR
FFTMR
Register bit number
B7
B6
B5
B4
B3
B2
B1
B0
Timer bit number
MDTMR
b3
MDTMR
b2
MDTMR
B1
MDTMR
b0
FFTMR
b3
FFTMR
b2
FFTMR
B1
FFTMR
b0
CMA3000-D01,
MODE bits x10
ODR: 400Hz
CMA3000-D01,
MODE bits x01
ODR: 100Hz
CMA3000-D01,
MODE bits 100
ODR: 10Hz
x=not used bit
1/400s =
2,5 ms
x
x
x
x
x
x
x
x
x
20
80
x
10
40
x
5
20
x
1/100s =
10 ms
1/10s =
100 ms
400
200
x
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