CMA3000-D01
SPI
VDD
1
2
DVIO
MISO
100n
100n
3
4
VDD
VSS
DVIO
MISO
INT
CSB
MOSI_SDA
SCK_SCL
8
7
6
5
INT
CSB
MOSI
DVIO
SCK
I2C
VDD
1
2
3
4
VDD
VSS
DVIO
MISO
INT
CSB
MOSI_SDA
SCK_SCL
8
7
6
5
SDA
SCL
INT
100n
100n
Figure 4
Application schematics for SPI and I
2
C bus
Note the
symmetrical
ground plane
under the
component.
Figure 5
Recommended layout pattern (not actual size, for reference only)
Table 1
Pin descriptions
Pin #
1
2
3
4
5
6
7
8
Name
VDD
VSS
DVIO
MISO
SCK_SCL
MOSI_SDA
CSB
INT
Function
Supply voltage
Ground
I/O Supply
SPI Serial Data Output (MISO)
SPI Serial Clock (SCK) / I
2
C Serial Clock (SCL)
SPI Serial Data Input (MOSI) / I
2
C Serial Data (SDA)
Chip select / I
2
C enable
Interrupt
Document Change Control
Rev.
0.1
…
0.7
0.8
0.9
0.10
0.11
0.12
0.13
0.14
Date
02-May-07
…
14-Feb-08
21-Apr-08
01-Jul-08
28-Aug-08
01-Sep-08
10-Dec-08
29-Dec-08
12-Jun-09
Change Description
1
st
version
…
Performance characteristics update
Target values for offset and sensitivity, non-linearity and cross axis added.
Figure 1 & Table 1 pin names corrected, Figure 2,3 & 5 updated
Current consumption, sensitivity and sensitivity temperature error, non-linearity,
cross axis sensitivity and noise updated.
8g range noise level corrected.
Performance characteristics and notes updated. Figure 2 updated.
Version for launch
Performance characteristics update
PRELIMINARY - Subject to changes
Doc. Nr. 8277800.14
4/4
Rev. 14
VTI Technologies Oy
www.vti.fi
VTI [ VTI TECHNOLOGIES ]
