Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
T6
T2
T7
T8
T1
T3
T4
T5
T0
CLK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
NOP
COMMAND
DQ’s
WRITE B
NOP
DINB
DINB
DINB
DOUT A
0
2
1
0
Must be Hi-Z before
the Write Command
: “H” or “L”
Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 3)
T6
T2
T7
T1
T3
T8
T4
T5
T0
1 Clk Interval
CLK
DQM
BANK A
ACTIVATE
NOP
COMMAND
WRITE A
NOP
NOP
READ A
NOP
NOP
NOP
CAS Iatency = 1
t
,DQ’s
DIN A
DIN A
DIN A
DIN A
CK1
DIN A
0
1
2
3
Must be Hi-Z before
the Write Command
CAS Iatency = 2
DIN A
DIN A
DIN A
0
1
3
2
t
,DQ’s
CK2
: “H” or “L”
Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 1, 2)
T6
T2
T7
T1
T3
T8
T4
T5
T0
CLK
DQM
NOP
COMMAND
NOP
WRITE B
NOP
NOP
READ A
NOP
NOP
NOP
CAS Iatency = 1
tCK1,DQ’s
DOUT A0
DIN B1
DIN B1
DIN B3
DIN B3
DINB2
DIN B0
DIN B0
Must be Hi-Z before
the Write Command
CAS Iatency = 2
tCK2,DQ’s
DIN B2
: “H” or “L”
Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 1, 2)
A read burst without auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS latency.
Document:
Rev.1
Page8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
