Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 22. Full Page Burst Read and Single Write Operation
(Burst Length = Full Page, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
High
CK3
CS
RAS
CAS
WE
DSF
BS
A9
RAv
A0 ~ A8
DQM0
RAv
CAv
CAw
CAx
CAy
DQM1~3
DQ0 - DQ7
Av2
Av2
Av2
Av2
DQx0
DQx0
Av1
Av1
Av0 Av1
Av0 Av1
Av3
Av3
Av0
Av0
DQw0
DQw0
Av3
Av3
DQ8 - DQ31
Single Write
Command
Bank A
Single Write
Command
Bank A
Burst Stop
Command
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Burst Stop
Command
Document:
Rev.1
Page48