Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 18.1. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
High
CS
RAS
CAS
WE
DSF
BS
RBx
RBx
RAx
RAx
RBy
RBy
A9
A0 ~ A8
CAx
CBx
tRP
tRRD
DQM
DQ
Hi-Z
Ax+2 Ax-2 Ax-1
Ax
Bx
Bx+5 Bx+6 Bx+7
Bx+4
Ax+1
Ax
Bx+2
Ax+1
Bx+1
Bx+3
Activate
Precharge
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
Command
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Activate
Full Page burst operation does not
Read
Command
Bank B
Command
Bank A
Burst Stop
Command
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Document:
Rev.1
Page40