Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 26.2. Precharge Termination of a Burst
(Burst Length = 8 or Full Page, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
DSF
BS
RAx
RAy
RAy
RAz
RAz
A9
CAy
RAx
CAz
CAx
A0 ~ A8
DQM
tWR
tRP
tRP
tRP
DQ
DAz0 DAz1
DAx1
DAz2
Ay0
Ay1
Ay2
DAx2
DAx0
DAx3
Activate
Command
Bank A
Read
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Command
Bank A
Precharge
Termination of
a Read Burst
Precharge Termination
of a Write Burst.
Write data is masked.
Document:
Rev.1
Page53
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
