Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 26.1. Precharge Termination of a Burst (Burst Length = Full Page, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
CS
RAS
CAS
WE
DSF
BS
RAx
RAx
RAy
RAy
RAz
RAz
A9
CAy
CAz
CAx
A0 ~ A8
DQM
tWR
tRP
tRP
Precharge
Termination of
a Read Burst
DQ
DAz0 DAz1 DAz2
DAx0
DAz4
DAz7
DAz5
DAx1 DAx2
DAx3
Ay0
Ay2
DAz3
DAz6
DAx4
Ay1
Read
command
Bank A
Precharge
Command
Bank A
Write
Precharge
Command
Bank A
Precharge Termination
of a Write Burst.
Write data is masked.
Activate
Command
Bank A
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Document:
Rev.1
Page52
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
