Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
(Burst Length = Full Page, CAS Latency = 2)
Figure 24. Full Page Random Column Read
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
DSF
BS
RBw
RBw
RAx
RAx
RBx
RBx
A9
CAx
CBx
CAy
CBy
CAz
CBz
A0 ~ A8
t
RP
DQM
DQ
t
RRD
t
RCD
Ay0 Ay1
Read
By0
By1
Az0 Az1 Az2
Ax0 Bx0
Bz1 Bz2
Bz0
Read
Command
Bank B
Read
Read
Command
Bank A
Activate
Activate
Command
Bank B
Command
Bank B
Command
Bank B
Precharge
Command Bank B
(Precharge Termination)
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Document:
Rev.1
Page50
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
