Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 23. Random Row Read (lnterleaving Banks)
(Burst Length = 2, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
CS
High
Begin Auto
Precharge
Bank A
Begin Auto Begin Auto Begin Auto
Precharge Precharge Precharge
Begin Auto Begin Auto
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Precharge
Bank B
Precharge
Bank A
Bank B
Bank A
Bank B
RAS
CAS
WE
DSF
BS
RBv
RBy
RBy
RBu
RAu
RAv
RBw
RBx
RAx
RAx
RAy
RAy
RBz
RAz
RAz
RAW
A9
CBw
RBw
CAy
RBz
RAv
CBy
CAu
RBv
CBv
CAv
CAw
CBx
CAx
CBz
RBu CBu RAu
RAw
RBx
A0 ~ A8
t
t
t
t
t
t
t
t
t
t
RP
RP
RP
RP
RP
RP
RP
RP
RP
RP
DQM
DQ
Av0 Av1
By0
Bu0
Au1 Bv0
Activate
By1
Bu1 Au0
Activate
Bv1
Bw0
Aw0 Aw1 Bx0 Bx1
Ax1
Bw1
Ax0
Ay0 Ay1
Bz0
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Activate
Command
Activate
Activate
Activate
Command
Bank A
Command
Bank B
Command Command
Bank A
Command Command Command
Bank A
Bank B
Bank B
Bank A
Bank B
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Document:
Rev.1
Page49
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
