Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 15.2. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
DSF
BS
RAx
RAx
RBw
A9
CBz
CAx
CBw
CBx
CAy
CBy
RBw
A0 ~ A8
tWR
tRP
tRP
t
RCD
DQM
DQ
t
RRD
Hi-Z
DBy1
DBy0
Write
DBz2
DBz1
DBx1
DAy0
Write
DBz0
Write
DBz3
DBw0
Write
DAy1
DAx3
DBx0
DBw1
DAx2
DAx1
DAx0
Precharge
Command
Bank B
Activate
Write
Activate
Command
Bank A
Write
Command
Bank B
Command
Bank A
Command
Bank B
Command Command
Command
Command
Bank A
Bank B
Bank B
Bank B
Precharge
Command
Bank A
Document:
Rev.1
Page32
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
