Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Random Row Write (Interleaving Banks)
Figure 12.3
(Burst Length = 8, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
BS
BS
RBx
RBx
RAy
RAy
RBx
RBx
A9
A0 ~ A8
CBx
CAx
CAy
tRCD
tWR
*
tW R*
tRP
DQM
DQ
Hi-Z
DBx3
DBx7
DAx5
DBx0
Write
DBx4 DBx5 DBx6
DAy1 DAy2 DAy3
Precharge
DAx0
Write
DAx4
DAx6
DBx2
DAy0
Write
DAx1 DAx2 DAx3
DAx7
DBx1
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Command
Bank A
Command
Bank B
Command
Bank A
Command
Bank B
*t
> t
(min)
WR
WR
Document:
Rev.1
Page24
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
