Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 26.3 Precharge Termination of a Burst
(Burst Length = 4, 8 or Full page, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
DSF
BS
A9
RAy
RAz
RAx
RAx
CAx
RAy
CAy
RAz
A0 ~ A8
t
tWR
tRP
RP
DQM
DQ
DAx0
Ay2
Ay0
DAx1
Ay1
Read
Command
Bank A
Precharge Termination
of a Write Burst
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Write Burst
Write Data
is masked
Document:
Rev.1
Page54