Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Read and Write Cycle (Burst Length = 4, CAS Latency = 1)
Figure 13.1
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK1
CS
RAS
CAS
WE
DSF
BS
RAx
A9
A0 ~ A8
CAz
CAx
CAy
RAx
DQM
DQ
Hi-Z
DAy3
DAy1
Az0
DAy0
Write
Az1
Az3
Ax0 Ax1 Ax2 Ax3
The Read Data
Read
Activate
Command
Bank A
The Write Data
is Masked with a
Two Clock
Latency
Command
Bank A
Command
Bank A
is Masked with a
Zero Clock
Latency
Read
Command
Bank A
Document:
Rev.1
Page25