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VG4632321AQ-45R 参数 Datasheet PDF下载

VG4632321AQ-45R图片预览
型号: VG4632321AQ-45R
PDF下载: 下载PDF文件 查看货源
内容描述: 524,288x32x2位CMOS同步图形RAM [524,288x32x2-Bit CMOS Synchronous Graphic RAM]
分类和应用: 内存集成电路
文件页数/大小: 81 页 / 1954 K
品牌: VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
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Preliminary  
VG4632321A  
524,288x32x2-Bit  
CMOS Synchronous Graphic RAM  
VIS  
T6  
T2  
T7  
T1  
T3  
T8  
T4  
T5  
T0  
CLK  
Bank  
Row  
Bank  
Col A  
Bank(s)  
ADDRESS  
t
RP  
READ A  
NOP  
COMMAND  
NOP  
NOP  
NOP  
Precharge  
NOP  
Activate  
NOP  
CAS Iatency = 1  
tCK1,DQ’s  
DOUT A  
DOUT A  
3
DOUT A  
DOUT A  
DOUT A  
0
1
0
2
CAS Iatency = 2  
DOUT A  
2
DOUT A  
DOUT A  
1
3
t
,DQ’s  
CK2  
CAS Iatency = 3  
,DQ’s  
DOUT A  
1
DOUT A  
2
DOUT A  
DOUT A  
3
0
t
CK3  
Read to Precharge (CAS Latency = 1, 2, 3)  
6
Read and AutoPrecharge command  
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A8 = ”H”, A0-A7 = Column Address, A9,A10 = Don’t  
care)  
The Read and AutoPrecharge command automatically performs the precharge operation after the read  
operation. Once this command is given, any subsequent command can not occur within a time delay of  
{t (min.) + burst length}. At full-page burst, only read operation is performed in this command and the auto  
RP  
precharge function is ignored.  
7
Write command  
(RAS = ”H”, CAS = ”L”, WE = ”L”, DSF = “L”, BS = Bank, A8 = ”L”, A0-A7 = Column Address, A9,A10 = Don’t  
care)  
The Write command is used to write burst of data on consecutive clock cycles from an active row in an  
active bank. The bank must be active for at least t  
(min.) before Write command is issued. During write  
RCD  
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data  
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs  
remains high-impedance at the end of the burst, unless other command was initiated. The burst length and  
burst sequence are determined by the mode register which is already programmed. A full-page burst will con-  
tinue until terminated (at the end of the page it will wrap to column 0 and continue).  
T6  
T2  
T7  
T8  
T1  
T3  
T4  
T5  
T0  
CLK  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
WRITE A  
NOP  
COMMAND  
DQ0 - DQ3  
DIN A  
0
DIN A  
DIN A  
don’t care  
DIN A  
1
2
3
Extra data is masked.  
The first data element and the write  
are registered on the same clock edge.  
Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3)  
Any Write performed to a row that was opened via an BankAcitvate & Masked Write Enable command is a  
masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the  
data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte  
basis, and the Mask register, which masks on a per-bit basis. This is shown in the following block diagram.  
Document:  
Rev.1  
Page9