VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note(1), (2))
DQM(7)
X
Command
State
CKEn-1 CKEn
BS
V
A9 A0-8 CS RAS CAS WE DSF
Idle(3)
BankActivate & Masked Write Disable
BankActivate & Masked Write Enable
H
H
X
X
V
V
V
V
L
L
L
L
H
H
H
H
L
Idle(3)
Any
X
V
H
BankPrecharge
PrechargeAll
Write
H
H
H
X
X
X
X
X
X
V
X
V
L
H
L
X
X
V
L
L
L
L
L
H
H
L
L
L
L
L
L
L
Any
Active(3)
Active(3)
Active(3)
Active(3)
Active(3)
H
Block Write Command
Write and AutoPrecharge
Block Write and AutoPrecharge
Read
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
L
H
H
L
V
V
V
V
V
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
Active(3)
Idle
Read and AutoPrecharge
H
L
Mode Register Set
H
H
X
X
X
X
V
X
L
V
V
L
L
L
L
L
L
L
L
L
Idle(5)
Any
Special Mode Register Set
X
H
No-Operation
Burst Stop
H
H
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
H
H
L
X
L
Active(4)
Any
Device Deselect
AutoRefresh
H
H
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
L
X
L
X
H
H
X
H
X
X
H
X
X
H
X
L
Idle
SelfRefresh Entry
SelfRefresh Exit
Idle
L
L
L
L
Idle
(SelfRefresh)
H
H
L
X
H
X
X
H
X
X
H
X
H
X
X
H
X
X
H
X
X
X
X
L
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any(6)
H
H
L
L
X
X
X
X
X
X
X
X
X
H
L
Clock Suspend Mode Exit
Power Down Mode Exit
Active
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
X
X
L
Any
(Power-
Down)
Data Write/Output Enable
Data Write/Output Disable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
Note: 1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not entry in the burst operation.
When this command assert in the burst cycle, device state is clock suspend mode.
7. DQM0-3
Document:1G5-0145
Rev.1
Page6
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
