VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Figure 5. Self Refresh Entry & Exit Cycle
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CLK
CKE
* Note 2
t
RC(min)
* Note 7
* Note 1
* Note 4
t
* Note 3
PDE
t
SRX
t
* Note 5
IS
* Note 6
CS
RAS
* Note 8
* Note 8
CAS
BS
A0 ~ A9
WE
DSF
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
Self Refresh Exit
Auto Refresh
Note: To Enter SelfRefresh Mode
1. CS, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays “low”.
Once the device enters SelfRefresh mode, Minimum t
is required before exit from SelfRefresh.
RAS
Note: To Exit SelfRefresh Mode
4. System clock restart and be stable before returning CKE high.
5. Enable CKE and CKE should be set high for minimum time of t
6 .CS starts from high.
.
SRX
7. Minimum t is required after CKE going high to complete SelfRefresh exit.
RC
8. 1024 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Document:1G5-0145
Rev.1
Page31
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
