VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
•
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page. But, lnterleave Mode only supports
burst length of 4 and 8.
A3
0
Addressing Mode
Sequential
1
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n+m), in the
table is larger than 255, only the least significant 8 bits are effective.
Data n
0
n
1
2
3
4
5
6
7
-
-
255
256 257
n+1
-
-
Column Address
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n+255
n
2 words:
4 words:
Burst Length
8 words:
Full Page: Column address is repeated until terminated.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the
address bits in the sequence shown in following table.
Data n
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Column Address
Burst Length
A7
A7
A7
A7
A7
A7
A7
A7
A6 A5 A4
A3 A2
A3 A2
A3 A2
A3 A2
A3 A2
A3 A2
A3 A2
A3 A2
A1
A1
A1
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
A0
A0
A0
A6 A5 A4
A6 A5 A4
A6 A5 A4
A6 A5 A4
A6 A5 A4
A6 A5 A4
A6 A5 A4
4 Words
8 Words
•
CAS Latency Field (A6 ~ A4)
This field specifies the number of clock cycles from the assertion of the Read command
to the first read data. The minimum value of CAS Latency depends on the frequency of
CLK. And this value satisfying the following formula must be programmed into this field.
t
CAC (min) £ CAS Latency x t
CK
A6
0
A5
0
A4
CAS Latency
Reserved
1 clock
0
1
0
1
X
0
0
0
1
2 clocks
0
1
3 clocks
1
X
Reserved
Document:1G5-0145
Rev.1
Page17
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
