VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
T6
T2
T7
T8
T1
T3
T4
T5
T0
CLK
NOP
COMMAND
NOP
NOP
NOP
WRITE A
NOP
READ B
NOP
NOP
CAS latency = 1
,DQ’s
DOUT B
DOUT B
DOUT B
DOUT B
DIN A
0
1
2
0
3
t
CK1
DOUT B
CAS latency = 2
DOUT B
0
DOUT B
DOUT B
3
DIN A
0
2
1
don’t care
don’t care
t
,DQ’s
CK2
CAS latency = 3
,DQ’s
DIN A
0
DOUT B
0
don’t care
DOUT B
DOUT B
2
DOUT B
3
1
t
CK3
Input data must be removed from DQ’
s at least one clock
cycle before the Read data appears on the outputs to avoid
data contention
Input data for the write is masked
Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without auto pre-
charge function should be issued m cycles after the clock edge at which the last data-in element
is registered, where m equals t /t rounded up to the next whole number. In addition, the
WR CK
DQM signals must be used to mask input data, starting with the clock edge following the last
data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll com-
mand is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
NOP
NOP
Activate
ROW
WRITE
NOP
COMMAND
ADDRESS
DQ
Precharge
BANK (S)
NOP
BANK
COLn
tWR
DIN
n
DIN
n+1
:don’t care
When Burst-Read and Single-Write mode is selected , the write burst length is 1 regardless of the
Write to Precharge
read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8
Block Write command
(RAS = “H” , CAS = “L” , WE = “L”, DSF = “H” , BS =Bank , A9 = “L” , A3-A7 = Column Address, DQ0-DQ31
= Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A single
data value, which was previously loaded in the Color register, is written to the block of eight consecutive col-
umn locations addressed by inputs A3-A7. The information on the DQs which is registered coincident with
the Block Write command is used to mask specific column/byte combinations within the block . The mapping
of the DQ inputs to the column/byte combinations is shown in following table.
Document:1G5-0145
Rev.1
Page12
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
