Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
Byte Write Operation
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High
CKE
CS
RAS
CAS
WE
BS
A10
RAa
CAa
CAz
RAa
CAb
ADD
LDQM
UDQM
Hi-Z
DQ0~DQ7
Hi-Z
DQ8~DQ15
Lower Byte
is masked
Read
Command
Bank A
Lower Byte
is masked
Upper Byte
is masked
Read
Command
Bank A
Write
Activate
Command
Bank A
Write Upper
is masked
Lower Byte
is masked
Command
Bank A
Document : 1G5-0127
Rev2
Page64